Senior ASIC Physical Design Engineer
Company: Google
Location: Sunnyvale
Posted on: April 1, 2026
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Job Description:
Minimum qualifications: Bachelor's degree in Electrical
Engineering, Computer Engineering, Computer Science, or a related
field, or equivalent practical experience. 7 years of experience
with physical design (e.g. from RTL to GDSII, including key stages
like floorplanning, place and route, and timing closure).
Experience in Python, Tcl, or Perl scripting. Preferred
qualifications: Experience working with external partners on
Physical Design (PD) closure. Experience in Static Timing Analysis
(STA), with an understanding of how to define timing corners,
margins and derates. Experience with Synopsys/Cadence PnR tools.
Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
Understanding of DFT including Scan, MBIST and LBIST. Understanding
of performance, power and area (PPA) trade-offs. About the job In
this role, you’ll work to shape the future of AI/ML hardware
acceleration. You will have an opportunity to drive cutting-edge
TPU (Tensor Processing Unit) technology that powers Google's most
demanding AI/ML applications. You’ll be part of a team that pushes
boundaries, developing custom silicon solutions that power the
future of Google's TPU. You'll contribute to the innovation behind
products loved by millions worldwide, and leverage your design and
verification expertise to verify complex digital designs, with a
specific focus on TPU architecture and its integration within
AI/ML-driven systems. As an ASIC Physical Design Engineer, you will
collaborate with RTL, Design for Testing (DFT), Floorplan, and
full-chip Signoff teams. Additionally, you will solve technical
problems with innovative micro-architecture and practical logic
circuits solutions, while evaluating design options with optimized
performance, power, and area in mind. The AI and Infrastructure
team is redefining what’s possible. We empower Google customers
with breakthrough capabilities and insights by delivering AI and
Infrastructure at unparalleled scale, efficiency, reliability and
velocity. Our customers include Googlers, Google Cloud customers,
and billions of Google users worldwide. We're the driving force
behind Google's groundbreaking innovations, empowering the
development of our cutting-edge AI models, delivering unparalleled
computing power to global services, and providing the essential
platforms that enable developers to build the future. From software
to hardware our teams are shaping the future of world-leading
hyperscale computing, with key teams working on the development of
our TPUs, Vertex AI for Google Cloud, Google Global Networking,
Data Center operations, systems research, and much more. The US
base salary range for this full-time position is $163,000-$237,000
bonus equity benefits. Our salary ranges are determined by role,
level, and location. Within the range, individual pay is determined
by work location and additional factors, including job-related
skills, experience, and relevant education or training. Your
recruiter can share more about the specific salary range for your
preferred location during the hiring process. Please note that the
compensation details listed in US role postings reflect the base
salary only, and do not include bonus, equity, or benefits. Learn
more about benefits at Google . Responsibilities Participate in the
Physical Design of complex blocks. Contribute to the design and
closure of the full chip and individual blocks from RTL-to-GDS.
Collaborate with internal logic and internal and external teams to
achieve the best Power/Performance Analysis (PPA). This includes
conducting feasibility studies for new microarchitectures as well
as optimizing runs for finished RTL.
Keywords: Google, San Rafael , Senior ASIC Physical Design Engineer, Engineering , Sunnyvale, California
